[DSM] 논문 : Sigma-Delta Modulators (4) Nonideal Performance and Systematic Design

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey 

 

 

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SECTION IV.

Nonideal Performance and Systematic Design

In previous sections, ΣΔMs have been considered ideal systems except for their inherent quantization error. In practice, such an ideal performance is degraded as a consequence of the circuit error mechanisms.14 Therefore, the impact of circuit nonidealities must be carefully considered during the design phase. This Section gives an overview of main ΣΔM circuit building blocks and their associated errors, with emphasis on their application to the systematic design of ΣΔMs.

 

A. Integrators and Resonators: Basic ΣΔM Building Blocks

A. Integrators and Resonators: Basic ΣΔM Building Blocks

Integrator circuits are the most important and critical building blocks of ΣΔMs [7], [14], [66]. Fig. 19 shows the integrator circuit topologies most commonly used in both DT- and CT-ΣΔMs. Fig. 19(a) shows a conceptual scheme of the well-known FE SC integrator, that implements a transfer function H(z)=z−1/(1−z−1). Fig. 19(b) and (c) show the conceptual schematics of the most frequently used CT integrators: Active-RC and Gm-C, respectively.15 Both CT circuits have an ideal transfer function H(s)=1/(τs), where τ is the time constant, which is the product of the resistive and capacitive elements of the CT integrator—shown in Fig. 19 for each type of implementation. In practice, the behavior of CT integrators involves a number of circuit design trade-offs. Thus, active-RC integrators present better linearity and larger signal swing, whereas Gm-C integrators usually can operate at higher frequencies [70].

 

Fig. 19.

Basic integrators in ΣΔMs. (a) SC FE. (b) Active-RC. (c) Gm-C.

As stated in Section III.D, the integrators which form the loop filter in LP-ΣΔMs become resonators in BP-ΣΔMs. There are many resonator filters using either DT or CT circuit techniques that have been included in ΣΔM ICs [25]. Fig. 20(a) shows the schematic of a SC fully differential implementation [71].16 Both resonator structures have a transfer function of the form H(z)=z−a/(1+z−2), which has poles located at zn=e(±jπ/2), that is, fn=±fs/4. This is a consequence of the aforementioned z−1→−z−2 (LP-to-BP) transformation method applied to integrators. In some applications such as multistandard wireless telecom systems, it is required to make the resonance frequency variable so that fn can be tunable (without changing fs) within a given band. This property can be implemented in the circuits shown in Fig. 20(a) by tuning capacitor ratios CAFB,AFB2/C. In the case of CT (Gm-C) resonators 17—conceptually depicted in Fig. 20(b)—the resonance frequency, given by fn=(1)/(2π)(gm2gmR)/(C1C2)−−−−−−−−−−−−−−√, can be electronically tuned by gmR [77].

 

Fig. 20.

Basic resonators in BP-ΣΔMs based on: (a) SC lossless direct integrators (LDIs) and FE integrators [71]; (b) Gm-C integrators [77].

 

 

B. Circuit Errors in ΣΔMs

B. Circuit Errors in ΣΔMs

There are a number of circuit nonidealities and nonlinearities causing a deviation from the ideal behavior of integrators and resonators. The way in which these nonidealities affect the performance of ΣΔMs depends on many different factors, among others: the nature of the error itself; the influence on a given subcircuit; the effect on NTF, etc.

 

In the case of SC implementations, main circuit effects can be grouped according to the ΣΔM circuit they affect as [7], [11], [27], [78]–​[80]:

• Amplifiers: Output swing, finite (linear and nonlinear) dc gain, dynamic limitations (gain-bandwidth, GB, and slew-rate, SR), thermal and flicker noise, etc.
• Quantizers: hysteresis, offset, and gain error.
• Capacitors: mismatch and nonlinearity.
• Switches: finite switch-on resistance, thermal noise, charge injection, clock feedthrough, nonlinearity.
• Multibit DACs: offset, gain error, and nonlinearity.

 

 

The above errors can be classified according to their effect on the modulator performance into two main families. On the one hand, those errors that change the NTF, such as the amplifier dc gain, capacitor mismatch, and incomplete integrator (linear) settling error. The effect of these errors strongly depends on the modulator topology. For instance, cascade ΣΔMs are more sensitive to capacitor mismatch and finite dc gain (often referred to as integrator leakage) than single-loop architectures. On the other hand, the second category of SC errors are those which can be modeled as additive noise sources at the modulator input and hence, they are not attenuated by the action of feedback. Among others, some errors belonging to this family are: clock jitter error, circuit noise (both thermal and flicker components), and harmonic distortion caused by circuit nonlinearities.

 

In the case of CT-ΣΔMs, circuit errors can be divided into two main categories [14], [66]:

• Building-block errors, which are the nonideal effects derived from the modulator loop filter implementation—similar to the SC case—such as finite opamp dc gain (for active-RC implementations), integrator time-constant error, integration incomplete transient response, circuit element tolerances, circuit noise, nonlinearities (especially those affecting front-end circuitry like input voltage-to-current Gm-C integrators), etc., [10], [66], [69], [81]–​[83].
• Architectural timing errors, namely: quantizer metastability, excess loop delay, and clock jitter error [10], [66], [84]–​[91].

 

 

The former group of errors cause similar effects on the performance of CT-ΣΔMs as in the case of their DT counterparts. Hence, they can also be classified according to the way they degrade this performance, either causing a deviation in NTF(f) or as additive noise sources. However as stated above, SC implementations have intrinsically lower parameter variations, since most circuit parameters are defined by capacitor ratios instead of absolute parameter values as it is the case of CT circuits. In contrast, CT implementations are potentially faster than SC ones, leading to much more relaxed designs (in terms of power consumption) when high-speed operation is required. For instance, it can be shown that the unity-gain frequency, fu, of active-RC integrators can be chosen to be in the range of fs, or even well below fs, depending on the chosen scaling coefficient [92]. However, typical requirements in DT-ΣΔMs lead to fu≃5fs [34].

 

In spite of the potential advantage of CT-ΣΔMs to operate at higher frequencies with less power consumption than their DT counterparts, their performance—particularly in high-speed applications—is largerly impacted by timing errors listed above. The first one—quantizer metastability—is essentially due to the variation of comparison time with the input signal—[85]. This effect can be circumvented by including latches between the quantizer and the feedback DAC. Clocking each latch stage on the opposite clock phase from the previous one gives the previous stage a good deal of time to settle. The price to pay is the additional delay introduced in the feedback loop [66]. Indeed, the effect of metastability is a critical issue as the clock frequency increases and the timing errors become limiting factors. However, the use of multiple latches has been demonstrated very effective even for sampling frequencies in the GHz range [93].

 

 

The second important timing error is caused by the delay introduced due to the finite transient response of the quantizer and the DAC circuitry in the modulator loop filter response [84]. This delay is often referred to as excess loop delay, and mathematically expressed as a fraction of the sampling period, i.e., τd=ρdTs. The excess loop delay error introduces additional poles that increase the order of both STF and NTF, which may lead to an unstable behaviour of the resulting CT-ΣΔM. In order to compensate for the effect of excess loop delay, a number of techniques have been reported in literature [94]. Among others, the most commonly used strategies are based on including additional feedback DACs—with their corresponding scaling coefficients—in order to cancel out the additional poles of NTF [53].

 

Among all timing errors affecting the performance of CT-ΣΔMs, the most critical one is caused by uncertainties in the clock-signal edges as illustrated in Fig. 21(a)—commonly referred to as clock jitter [66]. This error occurs at those points within the modulator architecture where signals are transformed from the CT- domain into the DT- domain and vice versa, i.e., at the S/H and reconstruction DAC, respectively as illustrated in Fig. 21(a). The error introduced by S/H is attenuated within the signal band by the modulator noise-shaping effect, and can hence be neglected. However, the jitter error at the DAC—illustrated in Fig. 21(b) for a NRZ and RZ waveforms—occurs without attenuation at the input node, thereby limiting modulator accuracy. The main reason why CT-ΣΔMs are more sensitive to clock jitter than DT-ΣΔMs is illustrated in Fig. 21(c), where a typical SC DAC waveform is compared to a CT current-mode waveform. Note that, in the SC case, most of the charge transfer occurs at the start of the clock period, so that the amount of charge lost due to a timing error is relatively small as compared to the total amount of transferred charge. By contrast, in CT-ΣΔMs, charge is transferred at a constant rate over a clock period, and hence, charge loss from the same timing error is a larger portion of the total charge [95]. The importance of clock jitter error has prompted a significant interest in the open literature as demonstrated by the large number of papers devoted to this topic [10], [66], [86] [87] [89], [91], [96], [97].

 

Fig. 21.

Clock jitter in CT-ΣΔMs. (a) Main error sources. (b) 1-bit RZ versus NRZ DAC waveforms. (c) DT versus CT feedback DAC waveforms.

 

 

The study of clock jitter and other nonlinear timing/architectural errors may require using specific analytical techniques like state-space formulation [86] and/or simulation-based analyses, in order to get semi-empirical closed-form design equations relating the error parameters with the effective resolution of the modulator. By contrast, in the case of those nonideal effects associated to building blocks, the general procedure commonly used to analyse their impact on the performance of the modulator is the following [7], [14]:

 

 

• Obtain an integrator equivalent circuit taking into account the nonideal effect under study.
• Analyse the impact of the nonideality on the integrator transfer function, i.e., H(z) for SC integrators and H(s) for CT integrators, such that H(z),H(s)→H(z,ϵ),H(s,ϵ), with ϵ being the error vector including all nonideal parameters involved in the integrator circuit equivalent obtained in previous step.
• In order to compute the effect of ϵ on a ΣΔM, the integrator transfer functions are replaced with H(z,ϵ),H(s,ϵ), and a linear model of the quantizer is consider to get the nonideal NTF, i.e., NTF(z,L,ϵ) and NTF(f,L,ϵ) for SC and CT ΣΔMs, respectively.

• The nonideal NTF is integrated within the signal band in order to obtain the in-band noise power as: PQ,ϵ=∫Signal Band(Δ2)/(12fs)|NTF(f,L,ϵ)|2df, which, after some approximations can be explicitly expressed as a function of ϵ and the modulator parameters, i.e., B,L,OSR. Note that, once PQ,ϵ is known, the corresponding nonideal expressions of DR and SNR can be obtained from their definitions given in (7), respectively.

 

 

 

 

A detailed description of the above procedure for each ΣΔM nonideality is beyond the scope of this paper and can be found in a number of manuscripts [14], [15]. However, it should be noted that the analysis of circuit errors is extremely important for a designer of ΣΔMs for three main reasons:

 

 

 

 

• First, it allows designers to obtain approximate design equations which, in closed-form, express the effect of each nonideality on the performance of both building blocks and the modulator themselves.
• Second, compact expressions that relate architectural parameters (L,OSR,B) with main circuit nonideal effects (mainly finite dc gain, capacitor mismatch, GB, and SR) and technological features can be used in a systematic design procedure to make accurate system-level estimations of the power consumption of different ΣΔM topologies. This analysis is usually done at the earlier phases of the design flow in order to decide the best ΣΔM architecture for a given set of specifications.
• Finally, a precise analysis of errors yield to the obtainment of accurate behavioral models that support fast and precise time-domain simulations, which constitute an essential part of the systematic design procedure of ΣΔ ADCs as detailed in the following sections.

 

 

C. Design Methodologies for ΣΔMs

The design of high-performance ΣΔ ADCs using nanometer CMOS technologies demands for proper design methodology and CAD tools which can optimize the design procedure in terms of efficiency and time-to-market deployment. To this purpose, a number of design methods and tools have been reported for the synthesis of ΣΔMs [7], [13], [98]–​[100]. The majority of them are based on the well-known top-down/bottom-up hierarchical design methodology [98]. The design process of a ΣΔM starts from the modulator specifications (essentially effective resolution and signal bandwidth). The first step is the selection of the modulator architecture and NTF that satisfy these specifications. At this step, ideal design equations like (4) and (7)—based on a linear model of the embedded quantizer—can be used to obtain approximate values for the main ΣΔM parameters (OSR, L and B). Once these values have been obtained, more accurate nonlinear models should be used. To this purpose, the well-known Schreier's MATLAB Delta-Sigma toolbox [13], [24] is widely used by the ΣΔM community. After the modulator architecture has been synthesized, the top-down design starts with the decomposition of the ΣΔM specifications into a subset of specifications for each system's building blocks. This procedure is known as translation or mapping of specifications. This process ends at the bottom level, where active (transistors) and passive (resistors, capacitors, and inductors) devices compose the lower level of abstraction of the blocks. The reverse path—the bottom-up process—begins by designing the individual cell-level blocks and ends with the assembly of the system-level circuit.

 

 

 

 

Fig. 22 shows an example of the application of the hierarchical top-down/bottom-up methodology to the design and synthesis of ΣΔMs [7]. At each hierarchy level, optimization can be combined with simulation to transmit the specifications to the lower level, i.e., to implement the sizing process at different levels of the modulator hierarchy. Two different synthesis tasks can be distinguished in Fig. 22, namely: high-level sizing and cell-level sizing. High-level sizing is the process by which building-block nonideal specifications (described in previous sections, like for instance opamp dc gain, output swing, GB, SR, etc.) are obtained as a function of the modulator-level specifications, i.e., effective resolution and signal bandwidth. In the next step, often referred to as cell-level sizing, an electrical (SPICE-like) simulator can be combined with an optimizer to find out the transistor sizes and biasing for given block specifications and minimum power consumption.

 

 

 

 

Note from Fig. 22 that at cell level, for each subblock, i.e., amplifiers, transconductors, comparators, capacitors, switches, etc. an appropriate topology and/or element arrangement need to be chosen and specification transmission at this lowest hierarchical level directly yield device sizes and bias voltages and currents. In practice, the implementation of this methodology takes into account multiple redesign iterations in case of performance specifications are not fulfilled. At each iteration, circuit performances are evaluated at a given point of the design parameter space. According to such an evaluation, a movement is generated in the design space and the process is repeated again [100].

 

 

 

D. Behavioral Modeling and Simulation of ΣΔMs

D. Behavioral Modeling and Simulation of ΣΔMs

The iterative nature of the synthesis procedure described above—usually needing a large number (hundreds or even thousands) of iterations—demands for efficient simulation techniques in terms of CPU time and accurate performance evaluation. In the case of ΣΔMs, long transient simulations are required to evaluate their main performance specifications because they are nonlinear oversampled-data systems. Therefore, transient analyses involving thousands of clock cycles are typically needed to obtain their main figures of merit, like in-band noise power or SNR. For this reason, transistor-level simulations using SPICE-like simulators yield excessively long CPU times—typically several days, or even weeks. To cope with this problem, different alternatives of dedicated simulators—based on using macromodels and/or multilevel simulation—have been developed, which at the price of reducing the accuracy in their circuit-element models, increase the simulation speed [7], [99], [101], [102]. Among others, one of the best accuracy-speed trade-offs is achieved by using the so-called behavioral simulation technique [102]. In this approach the modulator is broken up into a set of subcircuits, often called building blocks or basic blocks. These building blocks are described by equations that express their outputs in terms of their inputs and their internal state variables [98]. Thus, the accuracy of the simulation depends on how precisely those equations—considering the nonideal and nonlinear circuit error mechanisms discussed in previous section—describe the actual behavior of each building block [100], [103]–​[105].

 

 

 

 

Some authors have proposed different approaches for the implementation of behavioral modeling and simulation of ΣΔMs in the MATLAB/SIMULINK platform [100], [106]–​[108]. The use of SIMULINK for the behavioral modeling and simulation of SC ΣΔMs was first reported in [106] and [107]. The models included in this toolbox [109]—based on the interconnection of SIMULINK standard library blocks—are very intuitive and useful for system-level evaluation. The block library contains only SC circuit models, implemented using MATLAB (M-type) files, with the subsequent penalty in computation time [110], [111]. Another approach consists of using the so-called C-coded S-functions [112] to implement time-domain behavioral models in SIMULINK [100].18 The use of S-functions allows to decrease the computational cost to acceptable values for synthesis purposes. For example, the simulation of 216 clock periods of a cascade 2-1-1 SC ΣΔM considering behavioral models with all circuit nonidealities takes a few seconds and it is about 50 times faster than the approach based on using M-file models.

 

 

 

E. From Systems to Circuits

E. From Systems to Circuits

Once the modulator architecture satisfies the required specifications, the next step consists of translating the system-level behavioral model to a circuit-level design, firstly using macromodels and finally a transistor-level implementation. This way, ΣΔM designers can analyse and verify the modulator performance at different stages of the design phase, combining the effect of those building blocks which have been designed (at the transistor level) with those ones which have not been sized yet. To this purpose, electrical simulations—normally using SPICE-like simulators—are carried out to check the modulator performance during different steps of the design process, with no excessive CPU time—typically a few hours. At initial steps of the design procedure, only macromodels (that include main circuit error limitations) are used. In the end, all subcircuits have been sized and a complete transistor-level simulation is required in order to verify the performance of the whole modulator.

 

 

The cell-sizing process for different modulator subcircuits can be carried out by following an optimization-based procedure as illustrated in Fig. 22, in which building-block specifications—extracted from the high-level sizing process—are mapped into transistor sizing and biasing. At this design step, potential circuit candidates (for instance different OTA topologies) are explored and the effect of technology corners, temperature variations, and supply voltage tolerances are taken into account. The final verification of the whole modulator schematic must take into account worst-cases of different subcircuits in order to guarantee a correct performance of the circuit.

 

 

 

 

 

 

 

 

 

 

 

 

 

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https://ieeexplore.ieee.org/document/5672380